1. Field of the Invention
The present invention relates to sample and hold circuits used in high-speed high resolution analog-to-digital converters.
2. Related Art
Sampling distortion is one of the main causes of overall distortion performance of an analog to digital converter (ADC). The two main mechanisms for the sampling distortion are the following:
Track mode distortion: typically the sampled voltage onto the sampling capacitor follows the input voltage with a lag proportional to Ton=Ron*(Csamp+Cpar) (where Cpar is the parasitic capacitance from the source, drain junctions of the NMOS and PMOS devices in the switch to the bulk). Since Ron and Cpar of the switch vary with the signal for a CMOS switch, this causes track mode distortion.
Switch capacitor charge injection errors: in a normal CMOS sampling structure, by using non overlapping clocks and early and late phases to clock the summing junction switch and the signal conducting switch respectively the charge injection errors due to the signal conducting switch is prevented from appearing at the output. The charge injection errors due to the summing junction switches is to the first order signal independent and therefore does not lead to significant distortion. However, a second order effect which causes distortion is that even though the charge stored on the summing junction switch is signal independent, the manner in which the charge divides when that switch is turned off, depends on the impedance seen on the left and the right side of the switch. The impedance on the left side of the switch is signal dependent and hence the charge division becomes signal dependent. This again shows up as distortion at the output.
Bootstrapping has been used in an attempt to solve this problem. It results in very high linearity, but the extra bootstrap capacitor needed is usually very large and hence becomes very area intensive.
Regular CMOS switches have been used, which works for large supply voltages (Vdd=>5V), but cannot get very high linearity for Vdd<=3.3 V while trying to sample large input voltages (about 2–3 V peak to peak differential).
Replica bridge networks have been used to keep the signal side switch operating at a constant Ron. This approach results in high linearity, but the overhead of the replica network and the replica amplifiers is both area intensive and power hungry.